The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) memory devices and those devices incorporating embedded memory. More particularly, the present invention relates to an automatic delay technique for early xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d memory access operations in synchronous dynamic random access memory (xe2x80x9cSDRAMxe2x80x9d) devices and those ICs employing embedded SDRAM arrays.
xe2x80x9cReadxe2x80x9d and xe2x80x9cwritexe2x80x9d commands can only be given to dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) devices after the row address has been decoded, the appropriate word line (xe2x80x9cWLxe2x80x9d) selected, the proper bit line (xe2x80x9cBLxe2x80x9d) signal amplified and the applicable sense amplifier (xe2x80x9cSAxe2x80x9d) latched. The period of time between the bank select and read/write command assertion is commonly referred to as tRCD, or the row address strobe (xe2x80x9c/RASxe2x80x9d) to column address strobe (xe2x80x9c/CASxe2x80x9d) delay.
If a DRAM xe2x80x9creadxe2x80x9d or xe2x80x9cwritexe2x80x9d command is allowed to occur too early, data can be corrupted by what is generally termed a sense amplifier xe2x80x9cdisturbxe2x80x9d. This xe2x80x9cdisturbxe2x80x9d can cause an operational failure through the premature xe2x80x9creadxe2x80x9d of a selected column address, with a resultant failure in correctly reading that address. Alternatively, if a xe2x80x9cwritexe2x80x9d is allowed to occur too early, adjacent columns can fail due to the act of writing to a particular column before the sense amplifiers have had time to latch their data as a consequence of capacitive coupling to those adjacent columns.
In this regard, circuits have been developed for asynchronous (or non-clocked) DRAMs such as extended data out (xe2x80x9cEDOxe2x80x9d) and fast page mode (xe2x80x9cFPMxe2x80x9d) DRAMs wherein the column address strobe signal may be asserted early and the read/write and address information latched on the falling edge of the /CAS signal. Internally, a clock or other timer is used to xe2x80x9chold offxe2x80x9d the column select and data information until the sense amplifier has been latched. This effectively prevents the previously mentioned xe2x80x9cdisturbxe2x80x9d condition.
On the other hand, in synchronous (or clocked) DRAMs, double data rate (xe2x80x9cDDRxe2x80x9d) SDRAMs and most embedded DRAMs, no analogous technique has been employed and an early /CAS has not been permitted with the external column address and data information having to equal the device""s internal set-up requirements in order to prevent any array or sense amplifier xe2x80x9cdisturbsxe2x80x9d. Due to the nature of a clocked DRAM (or SDRAM), commands can be given only once per clock period. This quantizing effect raises the importance of the present invention since there may be cases with prior art SDRAMs where the /RAS to /CAS delay (tRCD) specification is just barely missed and the user is force to wait for an entire clock period to start a xe2x80x9creadxe2x80x9d or xe2x80x9cwritexe2x80x9d operation.
In accordance with the technique of the present invention disclosed herein, a circuit and method which controls the internal column select (xe2x80x9cYixe2x80x9d) and data signals is provided in conjunction with a synchronous DRAM array such that the /CAS signal is allowed to go xe2x80x9cactivexe2x80x9d in advance of that otherwise possible in conjunction with conventional SDRAM devices and other ICs having embedded SDRAM arrays.
In an exemplary embodiment disclosed herein, a system for implementing the technique of the present invention functions to delay the column select signal xe2x80x9cYixe2x80x9d (either the xe2x80x9creadxe2x80x9d column select signal xe2x80x9cYRixe2x80x9d or the xe2x80x9cwritexe2x80x9d column select signal xe2x80x9cYWixe2x80x9d) until either of the pre-decoded column address signals xe2x80x9cCA210xe2x80x9d (either the corresponding pre-decoded xe2x80x9creadxe2x80x9d column address signal xe2x80x9cCA210Rxe2x80x9d or the pre-decoded xe2x80x9cwritexe2x80x9d column address signal xe2x80x9cCA210Wxe2x80x9d) or the column clock signal xe2x80x9cPHIYBxe2x80x9d (either the corresponding column clock xe2x80x9creadxe2x80x9d signal xe2x80x9cPHIYBRxe2x80x9d or the column clock xe2x80x9cwritexe2x80x9d signal xe2x80x9cPHIYBWxe2x80x9d) is valid, whichever occurs later. Functionally, the PHIYB signal is delayed by the clock xe2x80x9cCLKxe2x80x9d or select xe2x80x9cSELxe2x80x9d (either the xe2x80x9creadxe2x80x9d select signal xe2x80x9cRSELxe2x80x9d or the xe2x80x9cwritexe2x80x9d select signal xe2x80x9cWSELxe2x80x9d), whichever is later. For the xe2x80x9cwritexe2x80x9d circuitry disclosed herein, the array select xe2x80x9cwritexe2x80x9d signal xe2x80x9cASELWxe2x80x9d output from the array select circuit is used, which signal goes xe2x80x9cvalidxe2x80x9d after the sensing begins. For the xe2x80x9creadxe2x80x9d circuitry disclosed herein, the array signal xe2x80x9creadxe2x80x9d signal xe2x80x9cASELRxe2x80x9d is used, which signal goes xe2x80x9cvalidxe2x80x9d a fixed delay after the sensing begins. This allows the sense amplifier latch nodes to separate before YRi goes xe2x80x9cvalidxe2x80x9d to ensure a fast read access time xe2x80x9ctACxe2x80x9d.
Particularly disclosed herein is a method for effectuating an access operation in a synchronous dynamic random access memory array arranged in rows and columns. The method comprises the steps of: awaiting an indication of a valid state of a pre-decoded column address signal for the access operation; also awaiting an indication of a valid state of a column clock signal and delaying a column select signal for the access operation until the later of a valid state of the pre-decoded column address signal or the column clock signal. In a more detailed implementation, the method further comprises the steps of: awaiting an indication of a valid state of an array select signal for the access operation; further awaiting assertion of a clock signal and delaying the indication of a valid state of the column clock signal until the later of a valid state of the array select signal or the clock signal.
When the access operation is a xe2x80x9cwritexe2x80x9d operation, the method may further comprise the steps of: detecting a sense amplifier enable signal to the memory array and indicating the valid state of the array select signal upon detection of the sense amplifier enable signal. When the access operation is a xe2x80x9creadxe2x80x9d operation, the method may further comprise the steps of: detecting a sense amplifier enable signal to the memory array and indicating the valid state of the array select signal a predetermined time period following detection of the sense amplifier enable signal.
Also disclosed herein is an integrated circuit device including a circuit for controlling a column select signal in a synchronous dynamic random access memory array. The circuit comprises: an array select circuit for receiving a sense amplifier enable signal and providing a first array select signal in response thereto; a first column clock circuit for receiving the first array select signal, a first column address signal and a clock signal with the first column clock circuit providing a first column clock signal in response thereto and a first access operation column decoder circuit for receiving the first column clock signal and a first pre-decoded column address signal and providing a first column select signal in response thereto.
In a more detailed implementation the circuit may comprise: a second column clock circuit for receiving a second array select signal from the array select circuit, a second column address signal and the clock signal with the second column clock circuit providing a second column clock signal in response thereto. A second access operation column decoder circuit is provided for receiving the second column clock signal and a second pre-decoded column address signal and providing a second column select signal in response thereto.